1. Field of the Invention
The present invention relates to a method and to an arrangement for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and to adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.
In the current technology, semiconductor devices are fabricated through the intermediary of a single one or a multiplicity of post exposure bake hotplates on the basis of pluralities of simultaneously operating semiconductor wafer production lines. In essence, in order to maintain the quality and uniformity of the formed image sizes for the integrated circuits of the semiconductor devices, presently proposed systems have implemented measures which are designed to control the temperatures of the post-exposure bake hotplates. Among the various systems utilizing hotplate temperature control for post-exposure baking in order to control image size are the applicant""s U.S. patent applications Ser. No. 09/314,368 and U.S. Ser. No. 09/361,451, which are commonly assigned to the assignee of the present application, and the disclosures of which are incorporated herein by reference. Both of these co-pending applications are directed to providing structure and methods for controlling the surface temperature of the hotplate which is used for post-exposure bake (PEB) so as to maintain the hotplate surface temperature variations within predetermined, narrowly specified bounds.
Virtually all deep UV (DUV) (248 nm), and subsequently developed lithography, such as those including 193 nm, EUV, X-ray and e-beam, employ chemically amplified resists. For chemically amplified resists, a typical process flow would essentially include the steps of:
1. Apply resist to wafer
2. Post-apply bake
3. Align/expose pattern
4. Post-expose bake
5. Develop pattern (ultimate image size).
The incident energy from the exposure releases a catalytic amount of acid, while the post-exposure bake (PEB) diffuses these acids, completes the desired chemical changes to the resist; in effect, either a deprotection for positive resist or a cross-linking for negative resists, and plays a major role in determining the ultimate resist image size. Resist image size response variations to the PEB can be substantial whereby typical numbers in the range of encountered variations are about 10-20 nm/(deg C).
As ground rules are tightened; for instance, such as sets of minimum feature sizes on a wafer, either in design or physically; essentially smaller semiconductor features which drive tighter tolerances, this places even more rigid demands on the precision in the temperatures of PEB hotplates. Even for current product, the range in variation for acceptable image size lots on some gate levels is less than 10 nm. This range in formation of image size is due to contributions from all kinds of effects, including exposure tool dose repeatability, developer normality, resist thickness, resist batch sensitivity repeatability, metrology, and PEB hotplate temperature. Consequently, the permissible contribution from any of these must be vanishingly small for acceptable manufacturability of the devices within specified production tolerances for the images on the wafers.
In addition to product quality requirements, there is also tremendous pressure in industry to increase throughput from lithography clusters. While some current DUV clusters provide for an output of about 30 wafers per hour (wph), new generation toolsets are presently being installed in industry wafer production lines which produce or even possibly exceed an output of about 80-100 wph. This averages out to a completed wafer being passed through the aligner every 35-45 seconds. However, the PEB processing step cannot be unduly accelerated or xe2x80x9crushedxe2x80x9d. Usually, this process step is fixed at a period of about one minute in order to provide an adequate process window and desired image characteristics. Thus, with the next generation of equipment, either the PEB must be allowed to gate the aligner, which is unlikely from an economic viewpoint since the wafer processing portion of the cluster is 5X less expensive than the aligner, or it becomes necessary to operate with more than one PEB hotplate; in essence, a plurality of wafer production paths.
However, operation with more than one PEB hotplate; i.e. in a plurality of concurrently operating wafer production paths, raises the extremely difficult problem of PEB hotplate matching. Typically combined accuracy/precision considered as a requisite for hotplate temperature tuning is on the order of +/xe2x88x920.5 deg. C. Hence, if two PEB hotplates are adapted at the extremes of this range, it is quite possible that product from the two hotplates would receive PEB""s which are an entire degree C apart, and thus would already be subjected to image size differences emanating solely from the PEB, of about 10-20 nm. This results in a completely unacceptable operating situation, so in fabricators running clusters with more than one PEB, frequent, high accuracy hotplate temperature checks are an absolute necessity. This procedure would most likely result in substantial time on the tool or tools being consumed with accuracy checks and adjustments instead of manufacturing throughput, thereby significantly adversely affecting the production economics.
2. Discussion of the Prior Art
Numerous publications pertaining to this technology address themselves in varying degrees of applicability to the problem of controlling image size of integrated circuits on wafers within specified bounds or tolerances; for example, during the post-exposure bake of integrated circuit-carrying wafers for semiconductor devices.
Ausschnitt et al U.S. Pat. No. 5,953,128 discloses a method of adjusting an exposure tool subsequent to the measuring of the dimensions of a developed image on a substrate of a semiconductor device. There is no disclosure of utilizing a post-exposure bake hotplate-specific dose feedback to provide for dosage control such that every path of a plurality of paths for the forming of specified image sizes on integrated circuit on semiconductor devices has the exposure adjusted so that all paths are at an optimum so as to be essentially indistinguishable from each other.
Dirksen et al U.S. Pat. No. 5,674,650 discloses a method of adjusting the illumination dose of an exposure tool based on a post-exposure bake. There is no feedback based on hot plate-specific conditions to vary the illumination dose whereby all paths of a plurality of wafer processing paths are adjusted so as to be optimally indistinguishable from each other.
Krivokapic et al U.S. Pat. No. 5,655,110 discloses a method of adjusting exposure following the measurements of images after etching. There is no dose feedback which is post-exposure bake hotplate-specific for a plurality of wafer processing paths which will render them optimally indistinguishable.
Marchman et al U.S. Pat. No. 5,656,182 and Hopewell et al. U.S. Pat. No. 5,124,927 each disclose adjusting the exposure tool and/or post-bake tool based on the measurements of latent images at each respective tool. There is no post exposure bake hotplate-specific dose feedback for a plurality of wafer processing paths product which is being processed. In particular, Marchman, et al., is directed to a process for fabricating a device wherein control is provided by a near-field imaging latent effect which is introduced into energy-sensitive resist material. This effects a control over resist process parameters, wherein one of the parameters relates to post-exposure baking.
Maeda U.S. Pat. No. 5,626,782 is concerned with a post exposure baking apparatus for forming fine resist integrated circuit line patterns on semiconductor wafers. In particular, this patent provides a capability for an evaluation in the changes of linewidth, and calculation methods for the temperatures in order to obtain desired linewidths for the integrated circuits, and for this purpose incorporates a plurality of heating components which are independently temperature-controlled.
Bohrer et al. U.S. Pat. No. 5,385,809 and Brown U.S. Pat. No. 5,286,607 each disclose photoresist materials which provide for minimum shrinkage to impose exposure bake. There is no disclosure of utilizing dose feedback which is hotplate-specific after post-exposure baking so as to be able to render every path of a plurality of wafer production paths adjustable so as to be optimally indistinguishable from each other.
Concerning various other patent publications, such as U.S. Pat. No. 5,139,904 this monitors the dimensions of feature on a wafer after exposure, post exposure baking development and etching; whereas U.S. Pat. No. 5,096,802 discloses controlled shrinkage of feature sizes at bake; U.S. Pat. No. 4,988,284 discloses predevelopment baking of photoresist layers for compensating for the e-beam proximity effect; U.S. Pat. No. 4,409,309 discloses controlled baking to obtain desired feature and image dimensions; and U.S. Pat. No. 4,264,712 discloses a method of circulating air over a hotplate at post-exposure bake to eliminate hot spots. None of these patents are directed to dose feedback determined in a hotplate-specific manner subsequent to post-exposure bake in order to adjust each and every path of a plurality of wafer production paths by adjusting the dose based on the path through the process, so as to render the output of each path in the forming of image sizes on the wafers identical to each other and close to a target value.
Although the foregoing manufacturing process in producing images on printed circuits is generally satisfactory in utilization with single hotplates, it is an intent of the invention to provide a system which, rather than utilizing sensors for controlling the temperature of the hotplate, particularly; for instance, where multiple post-exposure baking hotplates are adapted to be employed, for achieving a greater degree of uniformity in the image size of integrated circuits, by controlling the dosage of the ultraviolet radiation or illumination to which the integrated circuits are exposed prior to conducting the semiconductor devices onto specified wafer production paths of various multiple tools or hotplates. This is accomplished by post-exposure bake (PEB) hotplate-specific illumination dosage feedback, for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and to adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.
In essence, none of the prior art publications as described herein above are directed to the provision of multiple post-exposure hotplates being run in a cluster without prohibitive amounts of time having to be expended on hotplate temperature cross-calibration. In order to provide the foregoing processing advantages for high speed and multi-tool hotplate installations, the present invention is directed to a novel concept of providing illumination dose feedback which is hotplate-specific for post exposure baking.
Accordingly, pursuant to the inventive concept, in the fabrication of semiconductor wafers wherein it is intended to control the image size of integrated circuits on the wafers within specified parameters or tolerances so as to impart a high degree of precision to the wafer image sizes, for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and to adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value
It is accordingly an object of the present invention to provide an arrangement for the fabrication of semiconductor wafers wherein the image size of integrated circuits on the wafers is controlled through post-exposure bake hotplate-specific illumination dose feedback.
A further object of the present invention is to provide an arrangement for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and to adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.
A further object resides in the provision of a method for fabricating semiconductor wafers including the controlling of image size of integrated circuits on the wafers through post-exposure bake hotplate-specific dose feedback.
Another object resides in the provision of a method for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and to adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.